1. Field of the Invention
The invention relates to an integrated semiconductor memory circuit having one-transistor memory cells each containing one selection transistor and at least one memory capacitor, the memory cells being disposed in matrix-like fashion at intersection points of word lines and bit lines; each bit line being formed of two bit line halves; each memory cell being connected through its selection transistor to a respective bit line half; one electrode of the at least one memory capacitor being connected during operation to a plate potential of a predetermined value; at least one dummy memory cell containing at least one memory capacitor per bit line half, one electrode of the at least one memory capacitor being connected during operation to the plate potential; and a device for precharging the bit lines to a bit line potential. The invention also relates to a method for operating the circuit.
In integrated semiconductor memory circuits, it is generally conventional to preload the bit lines BL to a bit line potential VBL (which is generally referred to as a precharging operation or precharge potential), before a readout of data from the memory cells MC. The purpose served is to ensure that the read amplifiers SA (which after all are generally flip-flop circuits that operate differentially) are supplied effectively, after the readout for weighting and amplification of the reading signals, only with those reading signals, since the bit line potential VBL is present with the same value at both inputs of the read amplifiers SA and therefore is ignored by the differentially functioning read amplifiers SA. While in the past, either the supply voltage potential VDD or the reference potential VSS was usually applied as the bit line potential VBL, today a value is typically applied that is equivalent to half the difference between the supply voltage potential VDD and the reference potential VSS, or else in semiconductor memory circuits of the kind that operate with a so-called internal supply voltage potential VDDint internally of the circuit that is reduced as compared with the supply potential VDD applied to the finished component, the corresponding half difference between the internal supply voltage potential VDDint and the reference potential VSS is currently applied.
If the conventional semiconductor memory circuit also has so-called dummy cells, then conventionally they too are loaded to the bit line potential VBL.
Integrated semiconductor memory circuits, especially of the one-transistor memory cell type (so-called 1T DRAMs or embedded 1T DRAMs), are known to be vulnerable to so-called soft errors, or in other words alpha rays, which typically originate in the component housing being used. Experiments have shown that conventional semiconductor memory circuits react variously strongly to such alpha rays, depending on whether a datum was to be memorized as a physical 0 or as a physical 1 (a physical 0 can correspond to either a logical 0 datum or a logical 1 datum; the relationship depends on the particular circuitry chosen). It has been demonstrated that this is due to so-called weighting asymmetry of the reading amplifiers SA, so that a memorized datum of physical 0, for instance, cannot be read out with the same certainty and the same margin of safety as a memorized physical 1 datum, and vice versa. That means, however, that the danger of the occurrence of soft errors increases for one type of datum while it decreases for the other. That is undesirable, since what one wants is equally good security against soft errors for both types of datum.
A remedy that has presented itself is to enlarge the memory cell capacities, which would make the reading signal greater and thus make the semiconductor memory circuit more secure against soft errors. However, that course cannot be taken in practice because it would result in a lateral and/or three-dimensional enlargement of the memory cells, which given present demands for miniaturization of semiconductor memory circuits is undesirable (the consequence would be larger memory chips and possibly larger housings needed for them, which might then no longer meet prevailing standards).